The invention relates to a digital image signal recording and reproduction apparatus and a packet communication interface circuit for use in such an apparatus.
When video cassette recorders (VCR) for recording and reproducing an analog image signal are used for duplication, a recording VCR records an image signal by synchronizing to the reproduction timing of a reproducing VCR i.e. to frame timing. The reproduction VCR outputs a synchronizing signal which represents a frame timing of the reproduction VCR to the recording VCR for realizing the synchronization. The recording VCR recognizes a transmission timing of a frame based on the synchronization signal and records the image signal for every one frame unit.
When an analog image signal is used, transmission can cause degradation of the image. Degradation may be avoided by transmitting a digital image signal. A digital image signal is transmitted (a Digital VCR is used) via a digital interface, for example, a bus which corresponds to IEEE1394 standard. On this standard, several apparatuses, e.g. VCRs are connected each other by the bus (shared bus).
For duplication, the reproducing VCR transmits packets containing image signal data. At least some of the packets contain synchronization information, for example in the form of a clock counter value of the bus clock counter of a IEEE1394 standard bus, the clock counter value being sampled from the bus clock counter at an instant in time which is in a fixed relation to instant the beginning of the frame is read from the reproducing VCR.
The recording VCR receives the packets from the reproducing VCR and records the image signal data from the packets. In addition the recording VCR retrieves the synchronization information from the packets and synchronizes the recording mechanism, such as the scanning head, to this synchronization information.